1. Field of the Invention
The invention relates to a method of fabricating a static random static memory (SRAM), and more particularly to a method of fabricating a drive transistor for an SRAM.
2. Description of the Related Art
Random access memory (RAM) including SRAM and dynamic random access memory (DRAM) is one kind of volatile memory. SRAM uses the "on" or "off" status of its transistors to store information, while selective charge or discharge of each capacitor in the cell decides data storage for a DRAM. Generally, SRAM is characterized by high speed operation, low power consumption and simple operation, and also has advantages of easy layout and low refresh frequency when compared with DRAM.
FIG. 1 shows a circuitry diagram of an SRAM cell including a CMOS. This SRAM cell includes two load transistors UT1, UT2, two drive transistors DT1, DT2, and two access transistors AT1, AT2. The gates of access transistors AT1, AT2 are controlled by the word line (WL) and the drains thereof are connected to the bit line
The access transistors AT1, AT2 have to be turned on when a read operation is performed in an SRAM. In order to avoid the loss of data in the memory cell due to the read operation, the current drive capability of the drive transistors DT1, DT2 must be larger than that of the access transistors AT1, AT2. Therefore, the width/length ratio of the gate of the drive transistors DT1, DT2 must be larger than that of the access transistors AT1, AT2 in conventional technology so as to satisfy the requirements above.
However, when the capacity of the memory becomes larger and the size of the transistor becomes smaller, the thickness of the gate becomes thinner, resulting in a gate depletion effect. The gate depletion effect causes the efficient capacitance to become smaller and the current drive capability of the transistor to become smaller. As a result, the performance of the SRAM is reduced.